1. Field of the Invention
This invention relates to a clock and data recovery system, particularly to a clock and data recovery system using the time-division multiplexed manner to control the ratio of the two gm values, and using the chopper modulation technique to mitigate the input-referred offset of the gm cells.
2. Description of the Prior Art
The clock and data recovery circuit (abbreviated as CDR) is applied to the receiving interface of serial transmission, which is often completed by the digital circuit under lower frequency. The most common circuit is the digital phase locking loop (DPLL). However, in some high-speed applications, such as the optical fiber communication system, due to the clock frequency of transmitted data is quite higher, thus it is usually completed by the analog circuit. Most of existing products utilize BJT or BiCMOS process, the operation frequency is higher, the resistant ability is stronger for noise, and the performance is better. However, the shortcomings are high process cost, difficult integration, and higher consumption of current. In recent years, the CMOS process technology is progressed constantly, due to the CDR circuit often has to be integrated with other circuits, thus the CMOS with the advantages of low power consumption, low price, and easy integration can be considered as quite suitable. Following the popularization of multimedia application, the demand for the transmission of communication system or other digital information has increased day by day in recent years, so that the clock and data recovery circuit has quite big application space and plays more important role.
The clock and data recovery circuit usually needs very small jitter peaking to obtain better jitter conversion expression. However, the conventional clock and data recovery circuit uses the loop capacitor in the circuit, which occupies larger circuit area, particularly upon using a passive capacitor to reduce the noise.
FIG. 1 is a graph illustrating a conventional clock and data recovery circuit with the charge pump. The conventional clock and data recovery circuit uses a charge pump clock and data recovery circuit widely. Charge pump clock and data recovery circuit 100 includes a phase detector 102, a charge pump 104, a loop filter 106 and a voltage control oscillator 108. The phase detector 102 receives a data signal DATA and a local clock CLK, then compares the phase difference between data signal DATA and local clock CLK, in order to generate two control signals UP, DN. The phase detector 102 is a Bang-Bang Phase Detector or a Binary Phase Detector. The control signals UP, DN are used to control a set of switch 1042 and to turn on a set of current source 1044, so that the current I from the current source 1044 charges the loop filter 106 to generate output voltage V. Output voltage V controls voltage control the oscillator 108 to adjust the phase of local clock CLK, so that the local clock CLK can maintain a constant phase difference with respect to the local clock CLK. Loop filter 106 includes a resistor 1062 and a capacitor 1064, which is used to filter the current I generated by the charge pump 104, wherein the resistor 1062 is connected to the capacitor 1064 in serial, and another terminal of the capacitor 1064 is connected to a ground terminal. In addition, the loop filter 106 further includes a capacitor 1066, which is used to inhibit high frequency jitter, and another terminal of the capacitor 1066 is also connected to a ground terminal. Normally, the tolerance of capacitor 1066 is much smaller than that of the capacitor 1064, so the capacitor 1066 is neglected herein. In order to get a smaller jitter peaking, a big loop capacitor is installed as the capacitor 1064. It may remove the zero of loop transfer function to obtain a very low frequency. However, the shortcoming of the big loop capacitor is that it occupies larger area. Furthermore, when the data rate of the clock and data recovery circuit is very high, the design bottleneck will be encountered.
FIG. 2 is a graph illustrating a conventional gm clock and data recovery circuit. In order to solve the bottleneck of high-speed data rate, gm cell 204 is used to substitute the charge pump. As shown in FIG. 2, a gm clock and data recovery circuit 200 includes a gm cell 204, a loop filter 206 and a voltage control oscillator 208. The gm cell 204 has input voltage Vos, leakage current ileak and a gm unit 2042. The phase detector 202 receives a data signal DATA and a local clock CLK, then compares the phase difference between data signal DATA and local clock CLK, in order to generate two control signals. The loop filter 206 includes a resistor 2062 and a capacitor 2064, which is used to filter current I generated by the charge pump 204, wherein the resistor 2062 is connected to the capacitor 2064 in serial, and another terminal of the capacitor 2064 is connected to a ground terminal. The gm cell 204 is connected to the phase detector 202. Similar to the charge pump clock and data recovery circuit, in order to obtain a smaller jitter peaking, a big loop capacitor is installed as the capacitor 2064. It may remove the zero of loop transfer function to obtain a very low frequency. The hardware occupies larger area, and the cost is higher. However, compared to the charge pump clock and data recovery circuit, the gm clock and data recovery circuit does not need high-speed switching. Thus, its performance is satisfactory at high speed (several Gb/sec and greater than several Gb/sec). However, the gm clock and data recovery circuit has to solve the problems, such as leakage current and bias due to mismatch, larger area occupancy of gm unit, and large power loss etc.
Therefore, how to research and develop an innovative clock and data recovery circuit, so as to save the circuit area of gm-LPF will be a main disclosure of this invention.